Coherent Accelerator Processor Interface The Coherent Accelerator Processor Interface (CAPI) is a general term for the infrastructure of attaching a coherent accelerator to an IBM POWER® system. The main application is executed on the host processor with computation-heavy functions executing on the accelerator. The accelerator is a full peer to the host processor, with direct communication with the application. The accelerator uses an unmodified effective address with full access to the real address space. It uses the processor’s page tables directly with page faults handled by system software.
POWER8とFPGAの関係 POWER8 PHB : PCIe Host Bridge CAPP : Coherently Attached CPU Processor Proxy PHB PSL : Power Service Layer CAPP AFU : Accelerator Function Unit PCIe FPGA PSL AFU
PSL : POWER Service Layer POWER8 CPU PSLは、IBMが開発 PHB CAPP CAPI対応FPGAボードベンダから提 供される (IBMから供給) PCIe FPGA PSL AFU
PSL : POWER Service Layer The PSL provides the translation and interrupt services that the AFU needs. This is what the kernel interacts with. For example, if the AFU needs to read a particular effective address, it sends that address to the PSL, the PSL then translates it, fetches the data from memory and returns it to the AFU. If the PSL has a translation miss, it interrupts the kernel and the kernel services the fault. The context to which this fault is serviced is based on who owns that acceleration function. https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/pl ain/Documentation/powerpc/cxl.txt
AFU : Accelerator Function Unit POWER8 CPU AFUは、ユーザが開発 PHB CAPP HDL(Verilog HDL/VHDL)でなく、 HLSなどを使ってC/C++でも可能 PCIe FPGA PSL AFU
libcx POWER8 Applicationは、 libcxl (ユーザ空間) API => Application Linux CXLデバイスドライバ経由で libcxl FPGAのAFUにアクセスする CXL FPGA(AFU)独自の デバイスドライバは不要 PCIe FPGA PSL AFU