System-level ESD protection of high-voltage tolerant IC pins – A case study Mirko Scholz 1, Steven Thijs, Shih-Hung Chen 2, Alessio Griffoni, Dimitri Linten, Masanori Sawada 3, Gerd Vandersteen 1, Guido Groeseneken 2 imec, Kapeldreef 75, 3001 Leuven, Belgium (1) also at: Vrije Universiteit Brussels, Dept. ELEC, Brussels, Belgium; (2) also at: Katholieke Universiteit Leuven, Dept. ESAT, Leuven, Belgium; (3) HANWA Electronics Ltd., Wakayama, Japan email: firstname.lastname@example.org Zusammenfassung – Mit und ohne anliegende Versorgungsspannung wurde eine Systemebene-ESD Schutzlösung für HVT IC-Pins untersucht. Die transiente Wechselwirkung des untersuchten SCRs mit den Komponenten auf Systemebene muss sorgfältig geprüft werden, um einen thermischen Ausfall des SCR zu verhindern, wenn keine Versorgungsspannung angelegt ist und Latchup, wenn der SCR eingeschaltet ist. Abstract – A system-level ESD protection solution for HVT IC pins is studied without and with applied supply voltage. The transient interaction of the studied SCR with the off-chip components needs to be studied carefully to prevent a thermal failure of the SCR when no VDD is applied and latchup when the SCR is powered up.
selected test structure for the case that a supply 1 Introduction voltage is applied to it, followed by some Integrating high-voltage (HVT) circuitry into a conclusions. standard low-voltage CMOS process is one of the challenging tasks when System-on-chip (SOC) 2 Test structure, test board and solutions like line drivers, USB interfaces, display measurement setup drivers etc are implemented. These HV-tolerant (HVT) IC pins operate at higher supply voltages To study the system-level ESD robustness of (V HVT IC pins a standard Silicon-Controlled DD) then the used low-voltage technology. Due to the higher V Rectifier (SCR), manufactured in a 130 nm DD the classical ESD protection solutions of the used low-voltage process often do CMOS technology, has been selected. The not work. Moreover additional challenges can nominal supply voltages in this technology are 1.2 occur. For example, due to the higher V V and 3.3 V. Due to its high trigger voltage DD there is a higher risk for latch up when the circuit is (~ 15.5 V) during ESD stress and the absence of a powered up. gate oxide it can be safely used as an ESD protection for HVT circuitry. Due to their known In this paper, we demonstrate a system-level ESD latchup sensitivity SCRs are usually not used as a protection methodology for HVT IC pins using a standalone power clamp. In this study we use the test board and board-level components together SCR as a “latchup monitor” and thereby working with an on-chip protection device on-wafer. With as a replacement for a latchup sensitive circuit in a measurements and simulations the interaction real application. between on-chip and off-chip devices is analyzed. The presented methodology enables the study of The SCR used is measured on-wafer. The probe on-chip ESD protection devices under system- needles and probe holder parasitic are extracted level ESD stress conditions and their interaction beforehand  and included in the analysis to with board-level components even before IC determine the influence of the needle parasitic in packaging. the setup during ESD stress. Off-chip components are added to the SCR by connecting a dedicated First, we present the test structure and double layer test board (Figure 1) to the on-wafer measurement setup. In the following section the setup. The test board has been manufactured using protection methodology for the non-powered state an industrial PCB process and FR4 as board is demonstrated. Next we show how to protect the
material. The top layer contains the h PC P B C B traces e s V V DD T1 SCR 6 and the foot o pri r nt n s for r re r qui u red d boa o rd d comp m onents t s like k capa p cit i or o s, re r sis i tor o s and TVS S di d ode d s. The h e 5 botto t m m laye y r wo w rks k as gr g ound plane and is ] 4 connected with plated vi v a to t the t op l aye y r. t [A n 3 rre u C 2 SCR 1 TVS 0 0 5 10 15 20
Volt l ag a e g [V [ ]
Figure 2: 100ns TLP and 5 ns s vfT f LP L IV curves of SCR and TVS diode(On-Semi i E SD5Z5 Z .0T1 T ) Figure 1: Photo t of f te t st s t board r fo f r r sy s ste t m-level ESD experiments; TVSx : TV T S dio i de, Cx C : decoupling Be B cause s the TV T S S dio i de tr t igg g e g r vo v ltage g VT1 (6.2 V) capacitor, Rx: se s ri r a i l l components t s (E ( SD re r si s st s o t r, r is much lower than the VT1 of the SCR (15.5 V) ferrite bead), VDDx: opti t o i nal l su s pply l volt l a t ge in i p n ut, t , the TV T S S diode d sho h uld d shun u t n th t e sys y te t m-level ESD ESD_IN: N in i pu p t t fo f r r ESD D st s r t e r ss s and su s p u ply l volt l a t ge e stress current until 5.4 A A wi w thout u tr t igg g e g ring g the h e (optional), OUTx: outp t ut t to t wa w fe f r r pro r ber r (S ( MA M ) SCR. At A hi h gh g er curr r ent n leve v l the SCR will trigger The e use s d ES E D S D str t ess s sourc r e c s ar a e e a Tr T ans n mi m ssion- and goes into sna n pbac a k k thereby turning off the Line Pulse (TLP) and ve v ry r y fast (vf v ) f TLP L tester TVS diode. At A the mo m me m nt of snapba b ck the HANWA T-5000 for o extr t ac a tin i g g the e IV I curve v s s of o f curre r nt t thr h ough g th t e SC S R C R is s mu m ch high g er than the h the devices used. The system-leve v l ES E D S D stre r ss s s TLP failing current and ther e ma m l failure of the SCR source is a Hu H ma m n Met e al l Model e (HM H M) ) tes e te t r e will occur. HANWA HED-W5000M. Ne N xt to t cur u ren e t pr p obes e , , However, HMM me m asure r me m nts on the SCR a high g imp m edance pa p ssi s v i e v vo v ltage g probe is i s devi v ce wi w th the TVS S di d o i de in para r ll l el e show w connected to the SCR in a KEL E V L IN I configu g rat a ion o n different results. Al A rea e dy y at low w str t ess s leve v l the h e to capt p ure th t e tra r nsi s ent n behavi v or of th t e SC S R C R SCR turns on. Figure 3 show o s w the cur u rent n thr h ough g h during g dif i fe f ren e t str t ess s condit i io i ns an a d wi w t i h h the SCR device at a HM H M M stress level of 500 V different off-chip configurations. with the TV T S S dio i de in paral a le l l. The 1st pulse (region A) of the HM H M M curr r ent n is i condu d cte t d e d 3 Power-off protection mainly by the TVS diode. 2 3.1 Applying the SEED methodology SCR current HMM source In I wh w ite pa p per r 3  2 th t e In I dustr t y y Co C uncil i on ES E D S D 1.5 targe g t leve v ls l pro r pose s d th t e so call l ed d Sy S s y tem- ] effi f ci c ent n ES E D S D desi s gn g (SE S E E D E ) D me m thodology g y for the h e t [A n 1 design of off-chip ES E D S D prot o ect c ion o s me m eti t ng g rre u c A B system-level ESD specifications. To select a 0.5 suitable off-chip prot o ect c io i n n the e TLP L P IV I cur u ve v s of o f the on- and off-chip ESD protec e ti t on devi v ce c s ar a e r e 0 captur u ed an a d comp m ared. If I requi u red e addit i i t onal a off- 0 10 20 30 40 4 50 60 70 80 chip devi v ces e can a be e added e to obta t in the e desi s re r d e d Time m e [ns n ]
system-level protection level. Figure 3: Me M asu s re r d HMM M st s r t e r ss s curr r e r nt t and Figure 2 shows w the 100 ns of the SC S R C R and a a curr r e r nt t th t ro r ugh SCR C at t SCR C trigger level (0.5 kV); selected off-chip ES E D S D prot o ect c ion o devi v ce for 5 V region A: 1st puls l e s , re r gio i n B : 2 nd pulse applications. The selected d TV T S S di d ode tur u ns-on At low stress level the TV T S V S diode d tu t rns n -off before around 6.2 V. It has a ju j ncti t on ca c pac a it i ance c of o f the 2nd pulse (regi g on n B) B rises and the 2nd pulse 80 pF and a HMM/IEC61000-4-2 robustnes e s of o f flows mainly through the SCR (Figure 4). ±30 kV. Ho H we w ve v r at high g er str t ess s s leve v l the 2nd pulse is
share r d bet e we w en n the h SC S R C R and TVS S diode d indicating a turn-off of the h TV T S S diode d after the durat a ion n of t he HM H M c urr r en e t.
5 defined at the end of the vfTLP pulse where SCR voltage and current are more quasi-static. 4 HMM source TVS The vfTLP IV curve extracted with averaging ] 3 window I reaches already at low vfTLP stress t [A n level (1.6 A) the V rre T1 of the SCR. This agrees well u C 2 with the measured HMM peak current (1.65 A) at the SCR trigger level. By adding this transient 1 information the SEED methodology can be extended with data which is required to fully 0 0 500 1000 1500 2000 understand the interaction between on-chip and HMM pre-charge voltage [V]
ESD off-chip protection device. Figure 4: Currents at 30 ns: measured HMM The SCR triggering already at low stress level stress current and current through SCR; calculated impacts the system-level ESD robustness of the current through TVS diode device when the TVS diode is placed in parallel. The expected failure level from the SEED The triggering of the SCR already at low HMM methodology and by using the relation established stress level cannot be explained using only the in  would be 2.9 kV. However the real failure SEED methodology. Transient information like level with added TVS diode is only 2.1 kV (Table for example the voltage overshoot of the TVS 1). diode is required in addition to the TLP IV data. Figure 5 shows the vfTLP IV data of the Table 1: Failure level of standalone SCR and SCR with TVS diode in parallel (no V standalone TVS diode extracted with two different DD applied) averaging windows.
HMM [kV] 30 3.5 SCR standalone (measured) 1.4 SCR with TVS (measured.) 2.1 25 3 I II SCR with TVS 2.5 20 2.9 C ] u (predicted by SEED) 2 r [V r e e g 15 n t
lta [ 1.5 A o ] V 10 Most of the 2nd pulse current goes through the 1 SCR and only a smaller part is conducted by the 5 0.5 TVS diode. At a HMM stress level of 2.1 kV, the 0 0 0 0.5 1 1.5 2 residual current through the SCR causes thermal (a) Time [ns]
breakdown (Figure 6). V 5 T1 SCR 15 SCR standalone 1.4 kV 4 SCR with TVS, 2.1 kV averaging window I averaging window II ] ] 10 3 t [A n t [A n rre u 2 rre c u C 5 1 0 0 50 100 150 200 0 Time [ns] 0 10 20 30 40 50
(b) Voltage [V] Figure 5: vfTLP IV testing (pulse width: 2 ns; rise Figure 6: Current through SCR with and without time: 200 ps) of standalone TVS diode: definition TVS diode in parallel; stress level: failure level of averaging windows (a) and extracted vfTLP IV curves (b); averaging window I (0.3 ns to 0.6 ns) Similar to the triggering of the SCR at low stress and II (1.7 ns to 1.9 ns) level the sharing of the 2nd pulse current at higher stress level between SCR and TVS diode cannot Averaging window I is defined at the beginning of be explained by the SEED methodology. HMM the vfTLP pulse. Voltage and current have a more simulations are required which are demonstrated transient character. Averaging window II is in the following section.
3.2 Transient analysis with SPICE 35 simulations 30 simulated measured 25 3.2.1 Simulation setup ] [V 20 e To study the transient behavior of on- and off-chip g lta protection devices SPICE simulations are carried 15 o V out with LTSPICE (Figure 7). 10 HMM 5 tester IHMM 0 probe 0 10 20 30 40 50 60 Time [ns] needles (b)
ITVS ISCR Figure 8: Current through (a) and voltage (b) TVS SCR across the TVS diode, comparison measurements and simulations; stress level: 1 kV
The SCR is modeled by modifying a SPICE model of a commercial discrete SCR. This Figure 7: Simulation setup for transient analysis; behavioral model contains information like the IHMM – HMM current, ITVS – current through TVS trigger behavior, on-resistance and holding current diode, ISCR – current through SCR and gives a good approximation of the real device The HMM tester is modeled according to . The behavior in the transient domain. TVS diode is modeled with a standard SPICE Figure 9 shows the simulated and measured model based on the datasheet and TLP data. To voltage across the SCR. Measurement and approximate and model the overshoot of the TVS simulation data include the parasitic of the probe diode an inductance is added in series and its needle and probe needle holder. A good value matched to measurement data obtained from agreement for the voltage after snapback is the standalone TVS diode mounted in the test obtained. The overshoot before device snapback board. This simplification is used because the in the simulation is significant higher. This is TVS diode consists of only one physical diode attributed to bandwidth limitations of the voltage and it is used in reverse mode. probe used during the measurement. Figure 8 shows the voltage across the TVS diode 50 during simulated and measured HMM stress. simulated Similar current and voltage waveforms are 40 measured obtained with the simulated TVS model. ] 30 [V e g 4 lta 20 o 3.5 simulation V measurement 3 10 ] 2.5 t [A n 0 2 rre 0 10 20 30 40 50 60 u 1.5 Time [ns] C
1 Figure 9: Voltage across standalone SCR; 0.5 comparison simulation and measurement; stress 0 level: 0.5 kV 0 50 100 150 200 (a) Time [ns]
To verify the accuracy of the simulation setup, first the SCR triggering is simulated with the TVS diode in parallel. In Figure 10a the current through the SCR is shown for the stress level when the SCR turn on. In Figure 10b the current through the SCR at a higher stress level is plotted. For both stress level a good agreement between simulation and measurement is obtained.
1.4 30 1.2 simulation SCR measurement 25 TVS 1 ] ] 20 0.8 t [A [V n e g 15 rre 0.6 lta u o C V 0.4 10 V TVS T1 0.2 5 0 0 0 50 100 150 200 0 50 100 150 200 (a) Time [ns]
(b) Time [ns]
3.5 Figure 11: Simulated voltages across TVS diode and SCR: (a) stress level: 0.5 kV, (b) stress level: 3 simulation measurement 1.5 kV 2.5 ] t [A 2 The current distribution between the SCR and n rre TVS during HMM stress is directly influenced by 1.5 u C this device behavior. Figure 12a shows the current 1 through TVS diode and SCR when the TVS diode 0.5 turns off during the duration of the HMM pulse. 0 Only the 1st pulse of the HMM current is 0 50 100 150 200 (b) Time [ns]
conducted by the TVS diode. The 2nd pulse is fully conducted by the SCR. Figure 10: Current through SCR with TVS diode in 2 parallel: a) stress level: 0.5 kV, b) stress level: TVS 1.5 kV; comparison between measurement and 1.5 SCR simulation; no VDD ] 1 t [A 3.2.2 Transient analysis n rre For the transient analysis different pre-charge u 0.5 C voltages are simulated and the voltages and 0 currents at different locations in the schematic are extracted. Figure 11 shows the voltage across the -0.5 TVS diode and across the SCR for two pre-charge 0 50 100 150 200 (a) Time [ns]
voltages. The TVS turns-off at low stress level (Figure 11a). The low holding voltage of the SCR 5 and the voltage across the probe holder and probe TVS needle parasitic are not high enough to keep the 4 SCR TVS diode on. More voltage drops at a higher ] 3 stress level keeping the TVS diode also on during t [A n the duration of the 2nd pulse of the HMM current rre 2 u (Figure 11b). C 1 30 0 SCR 25 TVS 0 50 100 150 200 (b) Time [ns]
] 20 [V e g 15 Figure 12: Simulated currents through TVS diode lta o and SCR: (a) stress level: 0.5 kV, (b) stress level: V 10 V TVS 1.5 kV T1 5 Figure 12b shows the current distribution when 0 the TVS diode stays on during the 2nd pulse. The 0 50 100 150 200 (a) Time [ns]
1st pulse and the 2nd pulse are shared between SCR and TVS diode. The obtained results clearly show why the SEED methodology cannot be used. Depending on the
applied HMM stress the TVS diode can be turned At a HMM stress level of 800 V the SCR triggers off by the SCR snapback or stays on during the and goes into latchup (Figure 15 a). This is duration of the HMM stress. HMM simulations or indicated by a sudden drop of the supply voltage measurements are required to fully explain this and a strong increase of the supply current. The device behavior. fast rise time of the HMM current together with the intrinsic inductance of the capacitor used 3.3 Designing the system-level ESD cause a voltage overshoot which is not suppressed protection fully by the TVS diode. An additional current limiting resistor is required 14 to limit the residual current through the SCR to a 700V 12 safe value. The methodology in  is used to 800V latchup 10 I @ 600 V: < 1 µA calculate the required resistance value for the peak VDD ] I @ 800 V: 100 mA current of 8 kV HMM. The safe current level is [V 8 VDD e g taken at 2 A for the SCR. With this data, the on- lta o 6 V resistance of TVS diode and SCR and by applying 4 Kirchhoff’s current laws a resistor value of about 2 7.3 Ω is obtained. The closest available value in the lab was 8.2 Ω. With the added isolation 0 0 500 1000 1500 resistor the residual current through the SCR stays (a) Time [ns]
at a safe level even at 8 kV HMM stress (Figure 0.5 13). 700V 0.4 800V latchup 5 SCR standalone 1.4 kV 0.3 ] 4 SCR + TVS + RISO, 8 kV t [A n 0.2 ] rre u C 3 t [A 0.1 n rre u 2 0 c -0.1 1 0 500 1000 1500 (b) Time [ns]
0 0 50 100 150 200 Figure 15: Measured voltage across (a) and Time [ns]
current (b) through SCR before and during latchup Figure 13: Current through standalone SCR (failing waveform) and with added TVS diode and After turn-on the SCR snaps back to its holding ESD resistor voltage. Due to the low on-resistance after snapback the SCR conducts part of the HMM current and an additional current which is 4 Power-on protection discharged from the decoupling capacitor (Figure To study the behavior of the protected SCR under 15 b). Due to its low holding current of 25 mA the powered conditions a typical decoupling capacitor additional discharge current keeps the SCR in the (SMD1206, thick film, 1 µF) and a VDD source latched state even when the HMM current is fully (Agilent E3136A) with an additional 75 V decayed. Over a longer time scale the SCR discrete zener diode as blocking device are added continues staying in the latched state due to a to the setup (Figure 14). For all power-on testing permanent current flow from the power supply to the VDD is set to 5 V and the VDD compliance to the board which is sourced by the power supply to 100 mA. restore the programmed supply voltage. 4.1 SPICE simulation setup for transient analysis To analyze the interaction of the on-chip and off- chip components under powered conditions, SPICE simulations are carried out. The setup in section 3.2 is extended with the components Figure 14: Setup for power-on testing  which are required for the powered ESD testing (Figure 16).
3 HMM 2.5 Cdecoup 2 TVS ] t [A 1.5 n rre u 1 C 0.5
0 -0.5 Figure 16: Schematic of power-on simulation setup 0 50 100 150 200 Time [ns] in SPICE (a)
The zener diode is modeled with the same 3.5 HMM breakdown voltage (75 V) like during 3 Cdecoup measurements. The decoupling capacitor is 2.5 TVS modeled with its equivalent model which consists ] 2 [V e of the intrinsic inductance, the parasitic resistance g 1.5 tla o and the capacitance value. V 1 To verify the power-on simulation setup the 0.5 latchup situation is simulated. Figure 17 shows the 0 simulated voltage across and the current through -0.5 0 200 400 600 800 1000 the SCR before and during latchup. In the (b) Time [ns]
simulation the SCR latches at the same HMM stress level like in the measurements proving the Figure 18: Simulated currents before and during latchup: HMM current, current through accuracy of the simulation. decoupling capacitor and TVS diode 25 0.7 kV 4.2 Designing the system-level ESD 20 0.8 kV latchup protection for the power-on state ] 15 [V Going into latchup during ESD stress is not e g lta allowed for ESD power clamps. Therefore the o V 10 design target for the power-on state is to prevent triggering and subsequent latching of the SCR at a 5 HMM stress level of 8 kV. The SCR in this case study is used as a latchup monitor. Therefore the 0 0 20 40 60 80 100 Time [ns] latchup protection will be demonstrated with
board level components only. Figure 17: Simulated voltage across SCR before By using the presented SPICE simulation setup a and during latchup; VDD = 5 V protection solution preventing SCR triggering is With the simulation setup the current distribution designed. The proposed solution (Figure 19) between the off-chip components is extracted. consists of a ferrite bead which is added between Below the latchup trigger level (Figure 18a) most the TVS diode and one decoupling capacitor. of the HMM current is conducted by the decoupling capacitor. Only a small part of the 1st pulse is conducted by the TVS diode. During latchup (Figure 18b) the SCR triggers. When reaching its holding voltage the SCR and decoupling capacitor share first the HMM current.
After the decay of the HMM current the discharge current from the decoupling capacitor keeps the Figure 19: Protection solution with ferrite bead SCR on. The negative current in Figure 18 b and RC filter; RISO: 8.2 Ω; Cdecoup: 1 µF; ferrite indicates this current which flows from the bead: Tyco Electronics BMB1-J0070-B08 capacitor through the latched SCR. Ferrite beads are passive components which block high frequency noise in supply lines. The use of ferrite beads for preventing latchup has been
proposed before . However, a design transient interaction of the studied SCR with the methodology was not given. off-chip components needs to be carefully studied to prevent any low failure level of the SCR when The isolation resistor together with a second no V decoupling capacitor works as a RC filter. It DD is applied and moreover to prevent latch up when the device is powered up. It was directs most of the HMM current through the first demonstrated that the SEED methodology needs decoupling capacitor leaving only a small residual transient information in addition to the TLP IV current for the TVS diode, ferrite bead and second data to ensure a protection design which takes also decoupling capacitor (Figure 20). When into account the transient interaction of on-chip simulating the presented design no latchup occurs and off-chip ESD protection with other board- at a stress level of 8 kV HMM. level components. 30 30 By using a SPICE simulator together with suitable SCR voltage 25 25 current through C1 models for all on-chip and off-chip components 20 20 an ESD protection solution for the power-on state C ] during system-level ESD stress has been designed u 15 15 r [V r e e and experimental verified. g n t lta 10 10 [A o ] V 5 5 Literature 0 0  M. Scholz et al., “Calibrated wafer-level HBM measurements for quasi-static and -5 -5 0 50 100 150 200 transient device analysis”, in Proc. Figure 20: Simulated voltage across SCR and EOS/ESD Symposium, 2007, pp. 89–94 current through first decoupling capacitor (C1) when SCR is protected with presented protection  “White Paper 3 - System Level ESD, Part solution and powered-up to 5 V; stress level: 8 kV I”, Industry Council on ESD Target Levels, 2011 Figure 21 shows the experimental verification of the protection solution. At a HMM stress level of  G. Notermans et al, “HMM and TLP 8 kV and a supply voltage of 5 V no latch up in Correlation”, IEW, 2011 the SCR occurs.  M. Scholz et al, “On-wafer Human Metal Model measurements for systemlevelESD 10 analysis”, Proc. EOS/ESD Symposium, SCR voltage 8 2009, pp. 405–413 ]  S. Marum et al, “Protecting circuits from 6 [V e g the transient voltage suppressor's residual V lta DD o V 4 pulse during IEC 61000-4-2 stress”, Proc. EOS/ESD Symposium, 2009, pp. 377-386 2  M. Ker et al, “Component-Level Measurement for TLU under system-level 0 0 200 400 600 800 1000 Time [ns] ESD considerations”, IEEE Trans. on Figure 21: Measured voltage across SCR when Device and Materials Reliability, 2006, protected with presented protection solution and Vol. 6, No. 3, pp. 461-472 powered-up to 5 V, HMM stress level: 8 kV  Hsu et al, “Study of board-level noise filters All components of the proposed protection to prevent transient-induced latch-up in solution are typically used to decouple and CMOS integrated circuits during stabilize the voltage in supply lines and do not add EMC/ESD test”, in Proc. International any additional devices to the bill of material of a Zurich Symposium on EMC, 2006, pp. 533- application board. 536 5 Conclusions A system-level ESD protection solution for HVT IC pins has been studied without and with applied supply voltage. It has been found, that the